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Andrew Lauricella
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  • Resume
  • My works
    • Capstone - DAD Website
    • Storkbot
    • Code Compiler
    • Pacman AI
    • Ford-Fulkerson Max Flow
    • 4-bit CPU
    • Multi-Threading
  • README
  • Contact me
Andrew Lauricella
  • Home
  • Resume
  • My works
    • Capstone - DAD Website
    • Storkbot
    • Code Compiler
    • Pacman AI
    • Ford-Fulkerson Max Flow
    • 4-bit CPU
    • Multi-Threading
  • README
  • Contact me
  • More
    • Home
    • Resume
    • My works
      • Capstone - DAD Website
      • Storkbot
      • Code Compiler
      • Pacman AI
      • Ford-Fulkerson Max Flow
      • 4-bit CPU
      • Multi-Threading
    • README
    • Contact me

4-bit CPU

  • Completed project includes a defined instruction set, a dedicated ALU and memory management

  • The logic design was completed through Intel Quartus and later uploaded to a Terasic DE10-Lite FPGA development board to verify the final design.

Full Project Files

Simulated Test Timing Diagram

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